The present invention relates generally to integrated circuits, and more particularly to an integrated circuit system for processing and displaying video and graphics.
Video and graphics systems are typically used in television control electronics, such as set top boxes, integrated digital TVs, and home network computers. Video and graphics systems may have processing capabilities for decoding compressed video data such as MPEG-2 video data. During decoding of MPEG-2 video data in conventional systems, memory transfer inefficiencies exist because conventional memory organization and addressing schemes do not take into account memory access requirements for MPEG-2 video decoding.
This application includes references to both graphics and video, which reflects in certain ways the structure of the hardware itself. This split does not, however, imply the existence of any fundamental difference between graphics and video, and in fact much of the functionality is common to both. Graphics as used herein may include graphics, text and video.
One embodiment of the present invention is a method of accessing a memory for processing compressed video data including: requesting to transfer the compressed video data using one of a plurality of addressing patterns, reading the compressed video data from the memory using the addressing pattern if a read operation has been requested, and writing the compressed video data to the memory using the addressing pattern if a write operation has been requested. The compressed video data may include MPEG-2 video data containing HDTV data or SDTV data, and the addressing patterns may include predetermined addressing patterns as well as programmable addressing patterns. The use of the predetermined addressing patterns results in receiving the compressed video data in a predetermined order in a less number of clock cycles.
Another embodiment of the present invention is a video decoding system. The video decoding system includes a memory for storing compressed video data, a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from the memory. The video decoder requests to the memory controller to transfer the compressed video data using one of a plurality of addressing patterns.
Yet another embodiment of the present invention is a video and graphics system. The video and graphics system may be implemented on an integrated circuit chip. The video and graphics system includes a data transport processor for receiving a plurality of transport streams, a video transport processor for extracting the compressed video data from the plurality of transport streams and for storing the compressed video data in an external memory, a video decoder for decoding the compressed video data to generate decoded video data and for storing the decoded video data in the external memory, and a memory controller for transferring the compressed video data and the decoded video data in and out of the external memory. The video decoder uses a plurality of predetermined addressing patterns to request the compressed video data from the memory controller.